from the Technology Interface

The following is a VHDL listing and simulation of a 0 1 1 0 sequence detector. This listing includes the VHDL code and a suggested input vector file. In addition to giving the user more exposure to VHDL and sequential machines, this routine demostrates the use of an input vector file for driving the simulation.

entity flag is port (
     clk,x:    in bit;
     z:        out bit);
end flag;               -- detect a 0110 sequence

architecture mealy of flag is
     type states is (a,b,c,d,e);
     signal state:  states := a;  -- initial value is a
     signal next_state:   states := a;  -- initial value
begin
clock:  process(clk)
          begin
            if clk'event and clk = '1' then
            state < = next_state;
            end if;
          end process clock;
state_trans:  process(state,x)   --reacts to changes in state and x
          begin
            next_state < = state;  --update next state
            case state is
               when a => if x = '0' then
                         z < = '0';
                         next_state < =b;
                    else
                         next_state < = a;
                         z < = '0';
                    end if;
               when b => if x = '1' then
                         next_state < = c;
                         z < = '0';
                    else
                         z < = '0';
                         next_state < = b;
                    end if;
               when c => if x = '1' then
                         next_state < = d;
                         z < = '0';
                    else
                         next_state < = b;
                         z < = '0';
                    end if;
               when d => if x = '0' then
                         next_state < = e;
                         z < = '0';
                    else
                         next_state < = a;
                         z < = '0';
                     end if;
               when e => if x = '0' then
                         next_state < = b;
                         z < = '1';
                    else 
                         next_state < = a;
                         z < = '1';        
                     end if;
end case;
end process state_trans;
end mealy;

START 0 ;
STOP 1000 ;
OUTPUTS z ;
INPUTS x clk ;
PATTERN         % test every combination x %
            
0>    0 0
200>  0 1
400>  1 0
600>  1 1
800>  1 0
1000> 1 1    
1200> 0 0
1400> 0 1
1600> 0 0
1800> 0 1
2000> 0 0
3000> 0 0
;