The following is a VHDL listing and simulation of a 2-input XOR gate. The two inputs are "a" and "b". The output is "y". The entity is called TTL7486 since this is a VHDL implementation of the function of that device.

entity ttl7486 is port              
           (
           a,b: in bit;
           y: out bit
           );
end ttl7486;

architecture behavioral of ttl7486 is
begin
process(a,b)
       variable temp1: bit;
       begin
       temp1:= a xor b;
       y <= temp1;
end process;
end behavioral;