from the Technology Interface

The following is a VHDL listing and simulation of a negative edge triggered d-type flip-flop. This is your first building block to learn when constructing sequential machines.

library ieee;
use ieee.std_logic_1164.all;  -- Negative Edged Triggered DFF
	entity dflipn is port (
		 d,clk: in std_logic;
		 q:  out std_logic );
	end dflipn;

architecture example of dflipn is
	begin
	    process(clk) begin      -- make the process sensitive to the input clk
 	    if (clk'event and clk = '0') then   -- set the changes to the negative edge of clock  
  	    q <=d;
  	end if;
end process;
end example;





This simulation shows that the output "q" is assigned the value
of the input "d" on the negative edge of clock (clk) as defined by the
VHDL statement if (clk'event and clk = '0').