The following is a VHDL simulation of an 8-input NAND gate. The inputs are "a,b,c,d,e,f,g, and h" and the output is "y". The entity is called ttl7430 since this is a VHDL implementation of that device.

library ieee;
use ieee.std_logic_1164.all;

entity ttl7430 is port (
        a,b,c,d,e,f,g,h:	in std_logic;
        y:      out std_logic
        );
end ttl7430;

architecture behavior of ttl7430 is
begin
        y < = not(a and b and c and d and e and f and g and h);
end behavior;

The simulation result for the VHDL 8-input NAND gate.
The output "y" asserts low when all inputs are high.