from the Technology Interface

The following is a VHDL listing and simulation of an inverter. The input is "a" and the output is "y". The entity is called TTL7404 since this is a VHDL implementation of one functional gate of that device.

library ieee;
use ieee.std_logic_1164.all;

entity ttl7404 is port (
        a:     in std_logic;
        y:     out std_logic
        );
end ttl7404;


architecture behavior of ttl7404 is
begin 
        y < = not(a);
end behavior;

This is the simulation result of the ttl7404 VHDL file. Note that the output "y" is the opposite logic level of the input "a". The propagation delay, from input to output for the device is also shown.