VHDL Routines

the Technology Interface / Winter98

VHDL Sample Routine A 2-input AND gate from the Technology Interface

The following is a VHDL listing and simulation of a 2-input AND gate. The two inputs are "a" and "b". The output is "y". The entity is called TTL7408 since this is a VHDL implementation of one gate of that device.

library ieee;
use ieee.std_logic_1164.all;


entity ttl7408 is port (
        a,b:    in std_logic;
        y:      out std_logic
        );
end ttl7408;

architecture behavior of ttl7408 is
begin
        y <= a AND b;
end behavior;

The simulation result for the VHDL AND gate. The output "y"
asserts high when inputs a and b are both high.