This VHDL routine provides the code for a 4-bit magnitude comparator. The entity describes two 4-bit inputs "a" and "b" using the vector statement. The output is "z". Comment statements are preceded by --.

entity comp4 is port (
	a,b:  in bit_vector(3 downto 0);  -- deines a vector of 4 values a3 to a0, b3 to b0
	z:	out bit);
end comp4;

architecture behavioral of comp4 is	--  the architecture is being described by its behavior
begin
comp: process (a,b)	         --  comp is an optional label identifying the process
	begin
	if a=b then
		z < = '1';
	else z < = '0';
	end if;
end process comp;
end behavioral;