The following is a VHDL listing and simulation of a 2-input NAND gate. The two inputs are "a" and "b". The output is "y". The entity is called TTL7400 since this is a VHDL implementation of one gate of the function of that device. Comments are identified by -- followed by text.

entity ttl7400 is port			-- Each I/O signal is listed in the entity
       (
       a,b: in bit; 			-- The bit type means 1 and 0 only
       y: out bit
       );
end ttl7400;
architecture behavioral of ttl7400 is  	-- set of statements describing the function 
begin
process (a,b)				--  this ID's the signals which will execute the process
        variable temp1: bit;
        begin
        temp1:=a and b;
        y < = temp1;
end process;
end behavioral;

The VHDL simulation of the 2-input NAND gate. The output "y" asserts low when a = b.