Volume 4 No.2, Spring 2001 ISSN# 1523-9926

Two-Stage FET-BJT Transistor Amplifier Experiment

Bill Huffine
Associate Professor, Program Coordinator
Electronics Engineering Technology

ABSTRACT

This two-stage transistor amplifier illustrates the basic principles of operation of a common source FET stage and a common emitter BJT stage. The common source JFET stage, using self-bias, is used as the first stage to achieve a high input impedance for the amplifier. The second stage is a common emitter amplifier using voltage divider bias to provide additional voltage gain.

It is assumed that the student has had some background in basic transistor amplifier theory, including the use of AC equivalent circuits. After having done a complete prelab analysis, the student is expected to develop his or her own procedure for performing the lab experiment. The student should then analyze and thoughtfully summarize the results of the experiment in a written lab report.  The use of Electronics Workbench as a computer simulation tool is also strongly recommended to enhance the learning process.

PURPOSE OF EXPERIMENT

The purpose of the experiment is to investigate the operation of a two-stage FET and BJT transistor amplifier.

SOME BASIC CIRCUIT NOTES

1. The FET used here is an inexpensive small-signal n-channel JFET;  a MPF102 or equivalent could be substituted, if desired.

2. For prelab, you can assume some typical values as follows:  b = 100, IDSS = 10 ma, VGS c/o = -4V, gmo = 4.8 mmhos (recall gmo = gm at VGS = 0), and gm = 3.3 mmhos (mS) at the operating point IDQ

3. You can effectively "measure" the input impedance of the amplifier Zi by inserting a large test resistor in series with the input to the amplifier, and then measuring how much of the generator signal appears at the input of the amplifier; for example, if the input signal is reduced by one-half, then Zi = the test resistance.

4. You can determine the output impedance of the amplifier Zo by temporarily placing a load resistor across the output of the amplifier, and determining how much the output signal drops as a result of this load (note: you will need to measure both the unloaded and loaded output voltages to determine Zo).   For example, if the output signal drops by one-half, then Zo = the load resistance.

ELECTRONICS WORKBENCH (EWB) SIMULATION NOTE

For a more accurate JFET simulation, you may need to change the ideal default n-channel JFET model in EWB to use the following JFET parameters (to more closely simulate the specified FET, with a typical IDSS of 10 ma,  and a VGS c/o of  -4V):   “VTO” (JFET "threshold" or cutoff voltage) = -4V, and “Beta” (JFET "transconductance coefficient")  = 0.00063 A/V2.    (More information on these transistor parameters can be found in Electronics Workbench and Pspice reference books).

PRELAB

1. Draw a "voltage-controlled voltage source" (VCVS) model of a voltage amplifier, consisting of a dependent voltage source connected in series with a resistive Zo (output impedance), and a resistive Zi (input impedance) connected across the input terminals.  Using this model and some basic input and output voltage measurements, you can determine the Zand Zo of the amplifier.

2. Design (bias) the JFET stage using "midpoint bias" (ID = 1/2 IDSS), with RS @ 1/gmo, and VGS @ VGS c/o /3.4.    Also, design the second stage (calculate RE) for an IE of about 2 ma.   NOTE: use the nearest standard 5% resistor values!  Be sure to clearly show ALL your design calculations in your report!

3. Calculate the basic FET and BJT transistor dc terminal voltages and currents, and the following ac circuit parameters:           Av1, Av2, AV tot (total voltage gain), Zi (ckt), and Zo (ckt).

LAB

Build the circuit shown in Figure 1.  Before connecting up the ac input signal, verify that your measured DC voltages are reasonably close to the predicted values (if they are way off, you will need to troubleshoot the circuit before continuing).  Then connect a small ac sinewave input signal to the amplifier at a suitable frequency (a few kHz), and measure the voltage gain(s), and Zi and Zo.  Record the waveforms seen on the oscilloscope (use DC coupling to see the composite signals) at various points in the circuit.  Determine if your measured waveforms seem reasonable (close to expected).

Hypothesize how could significantly increase the voltage gain of this circuit.  Be sure to reduce Vi as needed to prevent overloading of the amplifier!

Record your results, and compare them to the predicted values (include a table of  % errors in your report).

Thoughtfully summarize what you have learned from this experiment by addressing the following issues:

• The advantages of using a FET for the first stage

• The purpose of the FET source bypass capacitor

• The type of coupling is used in the two-stage amplifier

• Your experimental results as compared to your predictions and computer simulations

Figure 1. FET - BJT "hybrid" 2 stage transistor amplifier

SUGGESTED REFERENCES

1. Floyd, Thomas L., Electronic Devices, Prentice Hall

2. Floyd, Thomas L., Fundamentals of Linear Circuits, Merrill

3. Boylestad, R. and Nashelsky, L. Electronic Devices and Circuit Theory, Prentice Hall

4. Stanley, William,  Operational Amplifiers with Linear Integrated Circuits, Prentice Hall

5. Tuinenga, Paul,  SPICE A Guide to Circuit Simulation and Analysis Using PSpice, Prentice Hall

6. Rashid, Muhammad, SPICE For Circuits and Electronics Using PSpice, Prentice Hall

7. Electronics Workbench reference books and transistor data sheets